 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Preliminary W91030B CALLING LINE IDENTIFIER Table of ContentsGENERAL DESCRIPTION ..............................................................................................................................2 FEATURES......................................................................................................................................................2 PIN CONFIGURATION ....................................................................................................................................3 PIN DESCRIPTION..........................................................................................................................................3 SYSTEM DIAGRAM ........................................................................................................................................5 BLOCK DIAGRAM ...........................................................................................................................................5 FUNCTIONAL DESCRIPTION ........................................................................................................................6 Ring Detector.................................................................................................................................................6 Input Pre-processor .......................................................................................................................................7 Dual Tone Alert Signal Detection....................................................................................................................7 FSK Demodulation.........................................................................................................................................9 Other Functions ...........................................................................................................................................11 ELECTRICAL CHARACTERISTICS..............................................................................................................13 Absolute Maximum Ratings .........................................................................................................................13 Recommended Operating Conditions...........................................................................................................13 DC Electrical Characteristics........................................................................................................................13 Electrical Characteristics - Gain Control OP-Amplifier ..................................................................................15 AC Electrical Characteristics........................................................................................................................15 AC Timing Characteristics ...........................................................................................................................16 APPLICATION INFORMATION .....................................................................................................................21 Application Circuit........................................................................................................................................21 Application Environment ..............................................................................................................................23 PACKAGE DIMENSIONS..............................................................................................................................29 The information described in this document is the exclusive intellectual property of Winbond Electronics Corporation and shall not be reproduced without permission from Winbond. Winbond provides this document for reference purposes of W-based system design only. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. -1- Publication Release Date: March 2000 Revision A1 Preliminary W91030B GENERAL DESCRIPTION The Winbond Caller Identification device W91030B, is a low power CMOS integrated circuit used to receive physical layer signals transmitted according to Bellcore and British Telecom (BT) specifications. There are two types of Caller Identifications, the first type is on-hook calling with caller ID message and the second type is call on waiting. The W91030B device provides all the features and functions of the Caller Identification specification for both these types, including FSK demodulation, Tone Alert Signal detection and ring detection. The FSK demodulation function can demodulate Bell 202 and CCITT V.23 Frequency Shift Keying (FSK) with 1200 baud rate. The Tone Alert Signal detect function can detect the dual tones of the Bellcore CPE* Tone Alerting Signal (CAS) and the BT idle State and Loop State Tone Alert Signal. The line reversal for BT, ring burst for CCA or ring signal for Bellcore can be detected by the ring detector. There are two modes of FSK data output interface. The first mode is a data transfer activated by the device, whose clock and data change depending upon the changing frequency of the FSK analog signal input. The second mode allows a microcontroller to extract 8-bit data from the device serially; the device notifies the micro-controller when 8-bit data has been received. Note: "CPE*" Customer Primises Equipment FEATURES * Compatible with Bellcore TR-NWT-000030 & SR-TSV-002476, British Telecom (BT) SIN227, U.K. Cable Communications Association (CCA) specification * Ring and line reversal detection * Bellcore CPE Alerting Signal (CAS) and BT idle State and Loop State Tone Alerting Signal detection use dual tone alerting signal detector * BELL 202 and CCITT V.23 FSK demodulation with 1200 baud rate * Use 3.579545 MHz crystal or ceramic resonator * Low power CMOS technology with sleep mode * High input sensitivity * Variable gain input amplifier * FSK carry detect output * Two modes for 3-wire FSK data interface * Packaged in 24-pin 0.6 inch (600 mil) plastic DIP (W91030B) and 24-pin 0.3 inch (300 mil) plastic SOP (W91030BS). Applications * Bellcore Calling Identity Delivery (CID), and BT Calling Line Identity Presentation (CLIP), CCA CLIP systems * Feature phones * Phone set adjunct boxes * FAX and answering machines * Data base telephone system and Computer Telephony Integration (CTI) systems -2- Preliminary W91030B PIN CONFIGURATION INP INN GCFB VREF CAP RNGDI RNGRC RNGON MODE OSCI OSCO VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 VDD ALGRC ALGR ALGO INTN FCDN FDRN DATA DCLK FSKE SLEEP/RESET TEST2 Top View 19 18 17 16 15 14 13 PIN DESCRIPTION PIN 1 2 3 NAME INP INN GCFB TYPE I I O DESCRIPTION Non-inverting Input of the gain control op-amp. Inverting Input of the gain control op-amp. Op-amp Feed-back Gain Control signal. Select the input gain by connecting this pin and the INN pin with a feed-back resistor. It is recommended that the op-amp be set to unity gain. Reference Voltage. Nominally, VDD/2 is used to bias the input of the gain control op-amp. Must be connected a 0.1 F capacitor to VSS. Ring Detect Input (Schmitt trigger input). Used for ring detection and line reversal detection. Must maintain a voltage between VDD and VSS. Ring RC (Open drain output and schmitt trigger input). Used to set the time interval from the end of RNGDI pin to the inactive condition of the RNGON pin. An external resistor must connected to VDD and a capacitor connected to VSS, the time interval is the RC time constant. Ring detection output (Low active). Indicates the detection of line reversal and/or ringing. FSK Data interface MODE select. Sets the FSK data output interface in mode 0 when low, or in mode 1 when high. Oscillator Input. A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCO pin. May be driven by an external clock source. 4 5 6 7 VREF CAP RNGDI RNGRC O O I O 8 9 10 RNGON MODE OSCI O I I -3- Publication Release Date: March 2000 Revision A1 Preliminary W91030B Pin Descriptions, continued PIN 11 NAME OSCO TYPE O DESCRIPTION Oscillator Output. A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCI pin. Should left open or to drive another clocked device when an external clock is connected to the OSCI pin. Power Supply Ground. Test pin. Must be connected to VSS for normal operation. Reset or Sleep Input (Schmitt input). When high the device will be reseted and enter a low power state by disabling the gain control op-amp, the oscillator and other internal circuits. The function of RNGDI, RNGRC and the RNGON pins are not affected when the device is in a sleep condition. This pin must be set low for normal operation. The device must reseted by micro controller or by external RC pulse after power on. FSK Enable. Must be set high when for FSK demodulation. May be set low to disable the FSK demodulator when FSK signal is not expected. Data Clock for the FSK interface. In the FSK data output interface mode 0 (MODE pin low), this pin is an output with a changing FSK frequency. In the FSK interface mode 1, this pin is an input. Data signal for the FSK interface. Serial data output according to the FSK frequency input in FSK data output interface mode 0 (MODE pin low). Data is shifted out on the rising edge of DCLK in FSK data output interface mode 1. Both logic 1 for mark and logic 0 for space. Data Ready of the FSK interface (Low active). In FSK interface mode 0 (MODE pin low), this pin identifies the 8-bit data boundary on the serial output string. In FSK interface mode 1, this pin is used to notify the microcontroller to extract the 8-bit data (ie. 8-bit data has been ready internally). FSK Carrier Detect (Low active). When low, it indicates the FSK signal has been detected. Interrupt signal (open drain). It is used to interrupt the microcontroller when RNGON or FDRN are low, or if ALGO is high. Remains low until all three signals have become inactive. Dual tone Alert signal Guard time detect Output. When high, a guard time qualified for the dual tone alert signal has been detected. Dual tone Alert signal Guard time Resistor. Also functions as a dual tone alert signal detect output without guard time. An external resistor must connected between this pin and ALGRC to implement guard time detection. Dual tone Alert signal Guard time RC (CMOS output and internal voltage comparator input). An external resistor must be connected between this pin and ALGR and an external capacitor between this pin and VDD to implement guard time detection. Power supply input. 12 13 14 VSS TEST SLEEP/ RESET I I I 15 16 FSKE DCLK I I, O 17 DATA O 18 FDRN O 19 20 FCDN INTN O O 21 22 ALGO ALGR O O 23 ALGRC I 24 VDD I -4- Preliminary W91030B SYSTEM DIAGRAM The W91030B device applications include telephone systems which have caller ID features and which can display the calling message on an LCD display. Figure 5 shows the system diagram. It illustrates how to use the chip to connect between the tip/ring and the microcontroller in the telephone system. The ring signal is detected by the W91030B device and then an interrupt sent to the microcontroller. The ring detected signal will also be directed to the ringer circuit. The data can be decoded by the microcontroller and displayed on the LCD display. The DTMF ACK signal can also be generated by the DTMF generator if a call on waiting is performed. Other functions are the same as the telephone set. LCD Display Keypads Tip Winbond Caller ID Micro Controller Ringer Speaker Ring Line Interface (W91030B) Handset DTMF Generator Figure 5. System Diagram for Caller ID Application BLOCK DIAGRAM FSKE Power down control Input Pre-processor FSK Demodulation Circuit FSK Bandpass Filter FSK Demodulator FSK Data Output Interface MODE INP INN GCFB VREF CAP SLEEP/ RESET VDD VSS + - Anti-alias Filter DCLK DATA FDRN FCDN FSK Carrier Detector To internal circuit Bias Voltage Generator High Tone Bandpass Filter To internal circuit Oscillator & Clock Driver Low Tone Bandpass Filter Power down control Dual Tone Alert Signal Detection Circuit High Tone Detector Guard Time Circuit Interrupt Generator INTN ALGO ALGRC ALGR Low Tone Detector Ring Detector OSCI OSCO RNGDI RNGRC RNGON Figure 6. The Block Diagram of W91030B -5- Publication Release Date: March 2000 Revision A1 Preliminary W91030B FUNCTIONAL DESCRIPTION Figure 6 is shown functional blocks of W91030B. The device must operate with a 3.579545 MHz system clock and consists four major functions and decribed as follows: Ring Detector The application circuit in Figure 7-1 illustrates the relationship between the RNGDI, RNGRC and RNGON signals. The three pin combination is used to detect an increase of the RNGDI voltage from ground to a level above the Schmitt trigger high going threshold voltage VT+. C1 = 0.1uF R1 = 470K V DD W91030B Tip/A R3 = 200 K RNGDI C1 = 0.1 uF R4 = 300 K Ring/B R2 = 470 K V DD R5 = 150 K RNGRC C3 = 0.22 uF Allowance minimal ring voltage (peak to peak) is: Vpp (max ring) = 2 (V T+(max) (R1 + R3 + R4) / R4 + 0.7) Tolerance to noise between Tip and Ring and Vss is: Vpeak (max noise) = V T+(min) (R1 + R3 + R4) / R4 + 0.7 Time constant is: T = R5 C3 ln [V DD / (V DD - V T+ )] V T+(min) <= V T+ <= V T+(max) RNGON R5 from 10K ohm to 500K ohm. C3 from 47 nF to 0.68 uF. Figure 7-1. Application Circuit of the Ring Detecter The RC time constant of the RNGRC pin is used to delay the output pulse of the RNGON pin for a low going edge on RNGDI. This edge goes from above the VT+ voltage to the Schmitt trigger low going threshold voltage VT-. The RC time constant must be greater than the maximum period of the ring signal, to ensure a minimum RNGON low interval and to filter the ring signal to get an envelope output. -6- Preliminary W91030B The diode bridge shown in Figure 7-1 works for both single ended ring signal and balanced ringing. R1 and R2 are used to set the maximum loading and must be of equal value to achieve balanced loading at both the tip and ring line. R1, R3 and R4 form a resistor divider to supply a reduced voltage to the RNGDI input. The attenuation value is determined by the detection of minimal ring voltage and maximum noise tolerance between tip/ring and ground. Input Pre-processor The input signal is processed by an Input Pre-Processor, which is added to the offset voltage to adjust the input amplitude and to filter out unwanted frequencies. The gain control op-amp is used to bias the input voltage with the VREF signal voltage. The voltage of VREF pin is VDD/2 typically, this pin had better connected a 0.1uF capacitor to VSS. It is also used to select the input gain by connecting a feedback resistor between this pin and the INN pin. Figure 7-2 shows the necessary connections with the tip/ring line inputs. In a single-ended configuration, the gain control op-amp is connected as shown in Figure 7-3. W91030B VREF VREF 0.1 uF R3 R4 0.1 uF W91030B C1 Tip R1 INP INN INP + - Input C R1 + INN - C2 R2 Ring R5 GCFB Voltage Gain Differential Input Amplifier C1 = C2 R1 = R2 R3 = (R4 R5) / (R4 +R5) Voltage Gain Av = R5 / R1 Input Impedance Zin = 2 2 R1 + (1 / wC)2 A V = R2 / R1 R2 GCFB Figure 7-2 Differential Input Gain Control Circuit Figure 7-3 Single-ended Input Gain Control Circuit Dual Tone Alert Signal Detection The dual tone alert signal is separated into high and low tones and detected by a high/low tone detector. The dual tone alert signal detection circuit is always enabled when the W91030B/BS is not in sleep state. The ALGR is the output of the dual tone detector and when high indicates that the high tone and low tone alert signals have been detected. The guard time improves detection performance by rejecting detected signals with insufficient duration and by masking momentary detection dropout. Figure 7-4 shows the relationship between the ALGR, ALGRC and ALGO pins and Figure 7-5 shows the guard time waveform of the same pins. The total recognition time is tREC = tDP + tGP, where tDP is the tone present detect time and tGP is the tone present guard time. The tone present guard time is the RC time constant with the capacitor discharging from VSS to VDD ( the ALGRC pin discharges from VSS to VDD through a resistor). The capacitor will discharge rapidly via a discharge switch after ALGO returns high. The total absent time is tABS = tDA + tGA, where tDA is the tone absent detect time and tGA is the tone absent guard time. The tone absent guard time is the RC time constant with the -7- Publication Release Date: March 2000 Revision A1 Preliminary W91030B capacitor charging from VDD to VSS (the ALGRC pin charges from VDD to VSS through a resistor). The capacitor will charge rapidly via a charge switch after ALGO returns low. To obtain unequal present and absent guard times, a diode can be connected as shown in Figure 7-6, to give the unequal resistance required during capacitor charging and discharging. W91030B Dual tone detected Capacitor Charge/Discharge Control Circuit Discharge Switch C VDD VDD ALGRC + Comparator V CPth R Charge Switch ALGR ALGO Figure 7-4. Guard Time Circuit of Dual Tone Alert Signal Detection Tip/Ring t DP Alerting Signal t DA ALGR t GP t GA ALGRC t REC V CPth VCPth ALGO Discharge Switch Charge Switch ON t ABS ON ON Figure 7-5. Guard Time Waveform of ALGR, ALGRC and ALGO pins -8- Preliminary W91030B W91030B V DD C ALGRC W91030B V DD C ALGRC R1 ALR R2 ALR R1 R2 (a) t GP > t GA t GP = R1 C ln [V DD / (V DD -V CPth )] t GA = R P C ln [(V DD -V D (R P / R2)) / (V CPth -V D (R P / R2))] R P = R1 R2 / (R1 + R2) V D = diode forward voltage (b) t GP > t GA t GP = R P C ln [(VDD -V D (R P / R2)) / (VDD -V CPth -V D (R P / R2))] t GA = R1 C ln [V / (VDD - V CPth )] DD R P = R1 R2 / (R1 + R2) VD = diode forward voltage Figure 7-6. Guard Time Circuits with Unequal Present and Absent Time FSK Demodulation The FSK demodulation circuit is enabled when the FSKE signal is high. An enable time is required to enable the FSK demodulator circuitry after the FSKE signal goes from low to high. FSK Carrier Detector The FSK carrier detector provides an indication of the presence of a signal within the FSK frequency band. If the output amplitude of the FSK bandpass filter is of sufficient magnitude and holds for 8 mS, the FSK carrier detect output signal FCDN goes low. FCDN will be released if the FSK bandpass filter output amplitude is of insufficient magnitude for greater than 8 mS. The 8 mS hysteresis of the FSK carrier detector is to allow for momentary signal drop out after FCDN has been activated. When FCDN is inactive, the output of the FSK demodulator is ignored by the FSK data output interface. In mode 0 of the 3-wire FSK data output interface, DCLK DATA and FDRN are all high and no clock and no data is driven. In mode 1, the internal shift registers are not updated, and FDRN is inactive (high state). The DATA is undefined if DCLK is clocked. 3-wire FSK Interface The 3-wire interface, DCLK, DATA and FDRN pins, form the data interface of the FSK demodulation. The DCLK pin is the data clock which is either generated by the W91030B or by an external device. The DATA pin is the serial data pin that outputs data to external devices. The FDRN pin is the data ready signal, also an output from the W91030B to external devices. There are two modes of this 3wire interface that can be selected. Mode 0, where the data transfer is initiated by the W91030B device, or Mode 1, where the data transfer is initiated by an external microcontroller. -9- Publication Release Date: March 2000 Revision A1 Preliminary W91030B Mode 0 (MODE = low): The W91030B processes the FSK signal and outputs signals on the DCLK, DATA and FDRN pins. Figure 7-7 shows the timing diagram of the 3-wire signals and the input of the FSK signal in mode 0. For each received stop and start bit sequence, the device outputs a fixed frequency clock string of 8 pulses on the DCLK pin. Each clock rising edge occurs in the middle of each data bit. DCLK is not generated for the stop and start bits. The DCLK pin is used as a clock driving signal for a serial to parallel shift register or for a serial data input for a microcontroller. After the 8-bit data has been shifted out by the device, the FDRN pin will supply a low pulse to inform the microcontroller to process the 8-bit data. start 1st byte data stop 1 start 0 2nd byte data stop start 0 b0 Tip/Ring 1* 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1* tIDD start 1st byte data b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 1 stop start 2nd byte data b0 b1 b2 b3 b4 b5 b6 b7 stop start DATA 1/fDCLK0 DCLK tCRD t RL FDRN * Mark bit or redundant stop bit(s), will be omitted. Figure 7-7. Serial Data Interface Timing of FSK Demodulation in Mode 0 Mode 1 (MODE = high): The W91030B processes the FSK signal and sets the FDRN pin low to denote the 8-bit boundary and to indicate to the microcontroller that new data has been transmitted. FDRN will return high on the first rising edge of DCLK. FDRN is low for half of a nominal bit time (1/2400 sec) if DCLK is not driven high. DCLK is used to shift 8-bit data out (LSB shift first) on the rising edge. After the last bit (MSB) has been read, additional clock pulses on DCLK are ignored. Figure 7-8 shows the timing diagram of the 3-wire signals and the input of the FSK signal in mode 1. - 10 - Preliminary W91030B Nth byte data (N + 1)th byte data stop start 0 b0 b1 b2 b3 b4 b5 b6 b7 stop 1 start 0 b0 1 Demodulated internal b6 bit stream b7 t RL FDRN Note 1 tDDS t DDH Note 2 DCLK 1/fDCLK1 DATA b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 Nth byte data b0 (N - 1)th byte data Notes: 1. FDRN cleared to high by DCLK. 2. FDRN not cleared, low for maximum time (1/2 bit width). Figure 7-8. Serial Data Interface Timing of FSK Demodulation in Mode 1 Other Functions Interrupt The interrupt INTN is an open drain output and is used to interrupt the microcontroller. Either RNGON low, FDRN low or ALGO high will set INTN low and will remain low until all of these three pins return to an inactive state. The microcontroller must read these pins to know what kind of interrupt occurred and to make the correct interrupt response. When the system is powered on, there is no charge on the capacitors. The voltage on the RNGRC pin is low and RNGON will be low. Also the voltage on the ALGRC pin is high and ALGO will be high if the SLEEP pin is low. This will cause an interrupt upon power up which will not be cleared until both capacitors are charged. The microcontroller should therefore ignore the interrupt from these source until the capacitors are charged up. The microcontroller can examine the RNGON and ALGO pins and wait until these signals are inactive during a power on interrupt. It is possible to clear the ALGO pin and its interrupt quickly by setting the SLEEP pin high. In the sleep mode, the ALGO pin is forced low and the charge switch in Figure 7-4 will turn on, forcing the capacitor to charge up rapidly. Sleep Mode The W91030B can go into a sleep mode by setting SLEEP high, resulting in reduced power consumption. In this mode, the gain control op-amp, oscillator and all internal circuits, except the ring detector are disabled. The RNGDI, RNGRC and RNGON pins are not affected, so the device can still react to call arrival indicators and activate an interrupt to wake up the microcontroller. The sleep mode can be disabled by the microcontroller. - 11 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B Crystal Oscillator The operation frequency of the W91030B is 3.579545 MHz. Crystal oscillators, ceramic resonators or other clock sources can be used. A crystal oscillator or ceramic resonator can be directly connected to the OSCI and OSCO pins without the need for external components. If other clock sources are used, the OSCI pin should be driven by a clock source and the OSCO pin used to drive other external clocked devices, or left open. Figure 7-9 shows some applications. The crystal specification is as follows: Frequency: Frequency tolerance: Resonance mode: Load capacitance: Maximum drive level (mV): 3.579545 MHz +/- 0.1 % (-40 C to +85 C) Parallel 18 pF 2 mV Maximum series resistance: 150 (a) With crystal osscillator or ceramic resonator W91030B OSCI OSCO 3.579545 MHz (b) With other clock source W91030B OSCI OSCO W91030B OSCI OSCO W91030B OSCI OSCO Oscillator OSCO 3.579545 MHz Figure 7-9. Some Application of Clock Driven Circuit Bias Voltage Generator The bias voltage generator provides a low impedance voltage source equal to VDD/2 and is used to bias the gain control op-amp. The voltage source is also used for internal circuits. A 0.1 F capacitor had better be placed between the VREF pin and VSS to reduce noise. - 12 - Preliminary W91030B ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltage referenced to VSS pin) PARAMETER Supply Voltage with Respect to VSS Voltage on Any Pin Other Than Supplies (Note 1) Current on Any Pin Other Than Supplies Storage Temperature Notes: SYMBOL VDD RATING -0.3 to 6 -0.7 to VDD + 0.7 0 to 10 UNITS V V mA C Tst -65 to 150 1. VDD +0.7 should not exceed the maximum rating of the supply voltage. 2. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Recommended Operating Conditions (Voltages referenced to VSS) PARAMETER Power Supplies Clock Frequency Clock Frequency Tolerance Operational Temperature SYMBOL VDD FOSC fC TOP RATING 3.0 to 5.5 3.579545 -0.1 to +0.1 0 to 75 UNIT V MHz % C DC Electrical Characteristics (VDD-VSS = 3.0V. The DC electrical characteristics supersede the recommended operating conditions unless otherwise stated.) PARAMETER Operating Supply Voltage Standby Supply Current CONDITION SYM. MIN. 3.0 TYP MAX. UNITS 5.0 1 2.6 1.6 4.1 2.5 3.7 2.3 5.9 3.6 mA A mA TEST/ NOTES Test 1 Test 2 IDDQ VDD = 3.0V FSKE = High IDD1 IDD2 IDD1 IDD2 Operating Supply Current VDD = 3.0V FSKE = Low VDD = 5.0V FSKE = High VDD = 5.0V FSKE = Low - 13 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B DC Electrical Characteristics, continued PARAMETER Schmitt Input High Threshold Schmitt Input Low Threshold CONDITION RNGDI, RNGRC SLEEP SYM. VT+ VTVHYS VIH VIL IOH MIN. 0.48 VDD 0.28 VDD 0.2 0.7 VDD VSS 0.5 TYP MAX. UNITS 0.68 VDD 0.48 VDD VDD 0.3 VDD V V TEST/ NOTES Schmitt Hysteresis CMOS Input High Voltage CMOS Input Low Voltage Output High Source Current DCLK, MODE, FSKE RGNON, DCLK, DATA, FDRN, FCDN, ALGO, ALGRC, ALGR RGNON, DCLK, DATA, FDRN, FCDN, ALGO, ALGRC, ALGR, INTN RNGRC INP, INN, RNGDI SLEEP, DCLK, MODE, FSKE RNGRC ALGRC INTN VREF VREF ALGRC V V mA Note 1 Output Low Sink Current IOL 0.5 mA Note 2 Input Current 1 Input Current 2 Output High-Z Current 1 Output High-Z Current 2 Output High-Z Current 3 Reference Output Voltage Reference Output Resistance Comparator Threshold Voltage IOL IIN1 IIN2 IOZ1 IOZ2 IOZ3 VRef RRef VCPth 2.5 1 10 1 5 10 0.5 VDD -4% 0.5 VDD -4% 0.5 VDD +4% 2 0.5 VDD +4% mA A A A A A V K V Note 2 Note 3, 5 Note 3, 5 Note 4, 5 Note 6 Tests: 1: All input pins are VDD or VSS except for oscillator pins, no analog inputs, output unloaded and SLEEP = VDD. 2: All input pins are VDD or VSS except for oscillator pins, no analog inputs, output unloaded, SLEEP = VSS and FSKE = VDD or FSKE = VSS. Notes: "" Typical figure are at VDD = 5V and temperature = 25 C are design aids only, not guaranteed and not subject to production testing. 1. VOH = 0.9 VDD. 2. VOL = 0.1 VDD. 3. VIN = VDD to VSS. 4. VOUT = VDD to VSS. 5. Magnitude measurement, ignore signs. 6. Output - no load. - 14 - Preliminary W91030B Electrical Characteristics - Gain Control OP-Amplifier (Electrical characteristics supersede the recommended operating conditions unless otherwise stated.) PARAMETER Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Ratio Maximum Capacitive Load (GCFB) Maximum Resistive Load (GCFB) SYM. IIN RIN VOS PSRR CL RL MIN. 10 TYP. MAX. 1 25 UNITS TEST CONDITIONS uA M mV dB 1 KHz 0.1 Vpp ripple on VDD VSS VIN VDD 40 100 50 pF K Note: "" typical figure are at VDD = 5V and temperature = 25 C are design aids only, not guaranteed and not subject to production testing. AC Electrical Characteristics (AC electrical characteristics supersede the recommended operating conditions unless otherwise stated.) Dual Tone Alert Signal Detection PARAMETER Low Tone Frequency High Tone Frequency Frequency Deviation Acceptance Frequency Deviation Rejection Maximum Input Signal Level Input Sensitivity Per Tone Reject Signal Level Per Tone Positive and Negative Twist Accept Noise Tolerance SNRTONE b SYM. FL FH MIN. TYP. 2130 2750 MAX. UNITS Hz Hz % % NOTES 1.1 3.5 0.22 -37 -45 7 20 -38 -44 1 2 a dBm 3 3, 4 3, 4 dBm dBm dB dB 3, 4, 5 Notes: a. dBm = decibels with a reference power of 1 mW into 600 ohms, 0 dBm = 0.7746 Vrms. b. Twist = 20 log (FH amplitude / FL amplitude). 1: The range within which tones are accepted. 2: The range outside of which tones are rejected. 3: These characteristics are for VDD = 5V and temperature = 25 C. 4: Both tones have the same amplitude. Both tones are at the nominal frequencies. 5: Band limited random noise 300-3400 Hz. Present only when the tone is present. - 15 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B FSK Detection PARAMETER Input Frequency Detection Bell 202 Mark (logic 1) Bell 202 Space (logic 0) CCITT V.23 Mark (logic 1) CCITT V.23 Space (logic 0) Maximum Input Signal Level Input Sensitivity Transmission Rate Input Noise Tolerance SNRFSK 1188 20 -43 1200 FMARK FSPACE FMARK FSPACE 1188 2178 1280.5 2068.5 1200 2200 1300 2100 1212 2222 1319.5 2131.5 -5.78 -45 1212 dBm dBm baud dB 1, 2, 3 1, 2 SYMBOL MIN. TYP. MAX. UNITS Hz +/-1% +/-1% +/-1.5% +/-1.5% NOTES Notes: 1. Both mark and space have the same amplitude and are at the nominal frequencies. 2. These characteristics are fort VDD = 5V and temperature = 25 C. 3. Band limited random noise 300 - 3400 Hz. Present only when the FSK signal is present. AC Timing Characteristics (AC timing characteristics supersede the recommended operating conditions unless otherwise stated.) System PARAMETER Wake-up Time Sleep-down Time SYMBOL tWAKE tSLP CONDITION SLEEP OSCO MIN. TYP. MAX. 50 1 UNITS NOTES mS mS Note: "" typical figures are for VDD = 5V and temperature = 25 C are design aids only, not guaranteed and not subject to production testing. Dual Tone Alert Signal Detection PARAMETER Alert Signal Present Detect Time Alert Signal Absent Detect Time SYMBOL CONDITION MIN. 0.5 0.1 TYP. MAX. UNITS NOTES 10 8 mS mS tDP tDA ALGR Note: "" typical figure are at VDD = 5V and temperature = 25 C are design aids only, not guaranteed and not subject to production testing. FSK Detection PARAMETER FSK Detection Enable Time Input FSK to FCDN Low Delay SYMBOL CONDITION MIN. TYP. MAX. 25 25 UNITS NOTES mS mS tFSKE tCP FSKE (high) - 16 - Preliminary W91030B FSK Detection, continued PARAMETER Input FSK to FCDN High Delay Hysteresis SYMBOL CONDITION MIN. TYP. MAX. 8 8 UNITS NOTES mS mS tCA FCDN Note: "" typical figure are at VDD = 5V and temperature = 25 C are design aids only, not guaranteed and not subject to production testing. 3-Wire Interface (Mode 0) PARAMETER Rise Time Fall Time Low Time Rate Input FSK to DATA Delay Rise Time Fall Time DATA to DCLK Delay DCLK to DATA Delay Frequency High Time Low Time DCLK to FDRN Delay tIDD tR tF tDCD tCDD fDCLK0 tCH tCL tCRD DCLK, FDRN DCLK DCLK DATA 6 6 1201.6 415 415 415 416 416 1202.8 416 416 416 1204 417 417 417 SYMBOL CONDITION tRR tRF tRL DATA FDRN 415 1188 416 1200 1 MIN. TYP. MAX. 200 200 417 1212 5 200 200 UNITS NOTES nS nS S bpS mS nS nS S S Hz S S S 4 4 1, 2, 3 1, 2, 3 2 2 2 2 4 4 2 1 Notes: "" Ttypical figure are for VDD = 5V and temperature = 25 C, are design aids only, not guaranteed and not subject to production testing. 1. FSK input data rate at 1200 +/-12 baud. 2. OSCI frequency at 3.579545 MHz +/-0.1%. 3. Function of signal condition. 4. 50 pF loading. 3-Wire Interface (Mode 1) PARAMETER Frequency Duty Cycle Rise Time DCLK Low Set-up to FDRN DCLK Low Hold Time After FDRN tR1 tDDS tDDH DCLK, FDRN 500 500 SYMBOL CONDITION f DCLK1 DCLK 30 MIN. TYP. MAX. 1 70 20 UNITS NOTES MHz % nS nS nS Note: "" typical figure are at VDD = 5V and temperature = 25 C are design aids only, not guaranteed and not subject to production testing. - 17 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B SLEEP t WAKE t SLP OSCO Figure 8-1. Wake up and Sleep Down Timing Tip/Ring Alerting Signal Alerting Signal ALGR tDP tDA tDP tDA Figure 8-2. Alert Signal Present and Absent Detect Timing Tip/Ring t FSKE Analog FSK Signal Analog FSK Signal FSKE Note tCA tCP tCA FCDN t CP Figure 8-3. FSK Detection Enable and FSK Carrier Detect Present and Absent Timing Note: The minimal delay from FSKE high to FCDN high is tFSKE + tCP, if the analog FSK signal is present before tFSKE has elapsed. tR tDCD tCDD tF VHM VCT VLM DATA tR tF DCLK t CL V HM = 0.7 VDD , VCT = 0.5 VDD , VLM = 0.3 VDD VHM VCT VLM t CH Figure 8-4. Data and DCLK Mode 0 Ouput Timing - 18 - Preliminary W91030B t RF tRR VHM VCT VLM FDRN t RL V HM = 0.7 VDD , VCT = 0.5 VDD , VLM = 0.3 VDD Figure 8-5. FDRN Output Timing 1st byte data start stop start 1 0 2nd byte data stop start 0 b0 Tip/Ring 1* 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1* tIDD 1st byte data start b0 b1 b2 b3 b4 b5 b6 b7 1 stop start 2nd byte data b0 b1 b2 b3 b4 b5 b6 b7 stop start DATA b0 b1 b2 b3 b4 b5 b6 b7 1/f DCLK0 DCLK t CRD tRL FDRN * Mark bit or redundant stop bit(s), will be omitted. Figure 8-6. Serial Data Interface Timing of FSK Demodulation in Mode 0 DCLK t R1 VHM VLM VHM = 0.7 VDD , VLM = 0.3 VDD Figure 8-7. DCLK Mode 1 Input Timing - 19 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B Nth byte data (N + 1)th byte data stop start 0 b0 b1 b2 b3 b4 b5 b6 b7 stop 1 tRL start 0 b0 1 Demodulated internal b6 bit stream b7 FDRN Note 1 t DDS t DDH Note 2 DCLK 1/f DCLK1 DATA b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 Nth byte data b0 (N - 1)th byte data Notes: 1. FDRN cleared to high by DCLK. 2. FDRN not cleared, low for maximum time (1/2 bit width). Figure 8-8. Serial Data Interface Timing of FSK Demodulation in Mode 1 - 20 - Preliminary W91030B APPLICATION INFORMATION Application Circuit Analog Interface The application circuit of the W91030B in Figure 9-1 shows the device being used within a typical CPE system. Note that only the circuit between the W91030B and the line interface is shown. The gain control op-amp is set to unity gain to allow the electrical characteristics to be met in this application circuit. It should also be noted that if a glitch with sufficient amplitude appears on the tip and ring interface, this will be detected as a ringing input by this circuit. +5V +5V 22nF Tip/A 430K 34K +5V +5V 0.1uF W91030B +5V 22nF Ring/B 430K 34K 53K6 60K4 0.1uF +5V 0.1uF +5V 470K 464K INP INN GCFB VREF CAP RNGDI RNGRC RNGON 200K MODE 150K OSCI 0.1uF 470K 300K 0.22uF OSCO VSS FSKE SLEEP/ RESET TEST VDD 10K ALGRC ALGR ALGO INTN FCDN FDRN DATA DCLK R1 R2 (This net must as short as possible) Must rest by microcontroller or by RC pulse. Resistor must have 1% tolerance. Resistor may have 5% tolerance. Crystal is 3.579545MHz with 0.1% frequency tolerance. R1, R2 must calculated according to the formula of Fig. 7-6 (a) for Bellcore or BT application. FSK 3-wire interface Mode 0 selected. Figure 9-1 Application Circuit Another application circuit for the W91030B, which provides common mode rejection of ringing circuit signals, is shown in Figure 9-2. When the AC voltage between the tip and ring is greater than the zener diode breakdown voltage, the photo-coupler LED will turn on, driving RNGDI high and thus detecting a ringing signal. Note however in this case, a glitch on the tip and ring interface is not able to turn on the photo-coupler and therefore will not be detected as a ringing signal. - 21 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B Application Information, continued +5V 22nF Tip/A 430K 34K +5V +5V +5V 0.1uF W91030B +5V 22nF Ring/B 430K 34K 53K6 0.33uF 0.1uF (This net INP 464K INN GCFB 60K4 must as short as VDD ALGRC ALGR ALGO INTN FCDN FDRN DATA DCLK FSKE SLEEP/ RESET TEST R1 R2 VREF CAP RNGDI +5V 0.1uF +5V RNGRC RNGON MODE 200K 12K + Vz 0.01uF 470K 150K OSCI 0.22uF OSCO VSS Must reset by microcontroller or by RC pulse. Resistor must have 1% tolerance. Resistor may have 5% tolerance. Crystal is 3.579545MHz with 0.1% frequency tolerance. R1, R2 must calculated according to the formula of Fig. 7-6 (a) for Bellcore or BT application. FSK 3-wire interface Mode 0 selected. Figure 9-2. Application Circuit with Improved Common Mode Noise Immunity Microcontroller Interface The following table is the requirement of micorcontroller I/O pin to interface with the W91030B: CASE 1 2 3 4 5 6 7 RNGON C C C C C C C SLEEP C C C C C C C FSKE C C H H H H H DCLK C C C C C C O DATA C C C C C C C FDRN C C C O C O O FCDN C O O O O O O INTN C C C C O O O ALGO C C C C C C C Note: "C" is connected with microcontroller, "O" is not connected with microcontroller, "H": this pin must set in high state. - 22 - Preliminary W91030B Case 1: This is the best case for microcontroller to monitor the W91030B, any condition can be monitored. Case 2: Analog FSK carrier detect output is not very important, FCDN pin can be ignored. Case 3: If FSKE pin is not controlled by microcontroller, this pin must set in high state and the FSK decode circuit is always active when W91030B is not in sleep state. The microcontroller must take care and ignore the false data when the FSK signal is not expected. Case 4: The FDRN pin is not very important during FSK decoding if INTN pin is used to interrupt the microcontroller. Case 5: If the microcontroller has no interrupt pin to use, any signal occurs of ringing, alert or byte boundary of FSK data can not notify the microcontroller, the microcontroller must always monitoring the RNGON, ALGO or FDRN. Case 6: If FDRN pin can not monitored by microcontroller and the microcontroller has no interrupt pin to use. In this case, the MODE pin must set low and the W91030B will drive DCLK pin. The microcontroller must track the timing of DCLK pin, it is a byte boundary if DCLK high for at least one bit width (1/1200 sec). Case 7: If FDRN pin and DCLK pin can not monitored by microcontroller and the microcontroller has no interrupt pin to use. In this case, the MODE pin must set low to set FSK data interface mode at mode 0 and the microcontroller must track the timing of DATA pin. The DATA pin will be toggled with 1/1200 second when FSK channel seizure input and stay in high state when FSK mark signal input, when FSK data input, start bit (low) follows bit 0, bit 1, ... through bit 7 then at least one bit of stop bit (high). The microcontroller must wait for the start bit and synchronize it, acquire each bit data at proper time and check the stop bit and then wait for next start bit arrival. The timer in the microcontroller must reset at the falling edge of the DATA pin after stop bit has been detected. Application Environment There are three major timing differences for caller ID sequences, Bellcore, BT and CCA. Figure 9-3 is the timing diagram for the Bellcore on-hook data transmission and Figure 9-4 is the timing diagram for the Bellcore off-hook data transmission. Figure 9-5 is the timing diagram for the BT caller display service on-hook data transmission and Figure 9-6 is the timing diagram for the BT caller display service off-hook data transmission. Figure 9-7 is the timing diagram for the CCA caller display service for on-hook data transmission. - 23 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B Tip/Ring 1st Ring A B Ch. seizure Mark C D Message E 2nd Ring F INTN ... ... RNGON SLEEP Note 1 Note 3 Note 4 Note 5 FSKE Note 2 FCDN FDRN ... ... DCLK DATA ...101010... Data Figure 9-3. Input and Output Timing of Bellcore On-hook Data Transmission A = 2 sec typical B = 250-500 mS C = 250 mS D = 150 mS E = Depends on data length MAX C + D + E = 2.9 to 3.7 sec F 200 mS Notes: 1. The CPE designer may choose to wake up the W91030B only after the end of the RNGON signal to conserve power for a battery operated CPE. The delay from RNGON to SLEEP (and FSKE) is the reactive time of the microcontroller. 2. The CPE designer may choose to set FSKE to be always high while the CPE is on-hook when the FSK signal is expected. 3. The microcontroller places the W91030B in a sleep condition after the last byte (check sum) has been decoded or FCDN has become inactive. 4. The W91030B may not be woken up at this ring signal after the FSK data has been processed. 5. If the W91030B has been woken up at the 2nd ring, the microcontroller times out if FCDN is not activated and then puts the W91030B into a sleep condition. - 24 - Preliminary W91030B CPE goes off-hook CPE mutes handset & disables keypad CPE sends CPE unmutes handset and enables keypad Mark Message F G Tip/Ring Note 1 CAS A B ACK C D Note 5 E SLEEP INTN t REC ... t ABS ALGO FSKE Note 2 Note 3 Note 4 FCDN FDRN ... DCLK DATA Data Figure 9-4. Input and Output Timing of Bellcore Off-hook Data Transmission A = 75-85 mS C = 55-65 mS E = 58-75 mS G 50 mS Notes: B = 0-100 mS D = 0-500 mS F = Depends on data length 1. In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and use battery power while on-hook. 2. The FSKE pin may be set low to prevent the alert tone, speech or other FSK inband noise decoded by FSK demodulator and give false data when the dual tone alert signal is expected. If the FSKE pin can not controlled by microcontroller, the FSKE pin must always placed in high state and the microcontroller must give up the FSK decoded data when the FSK signal is not expected. 3. FSKE should be set high as soon as the CPE has finished sending the acknowledge signal ACK. 4. FSKE may be set low after the last byte (check sum) has been decoded or FCDN has become inactive. 5. For unsuccessful attempts where the end office does not send the FSK signal, the CPE should disable FSKE, unmute the handset and enable the keypad after this interval has elapsed. - 25 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B Line Reversal A/B Wires A Alert Signal B C Ch. Seizure D Mark E Message F Ring G RNGON SLEEP Note 4 INTN tREC tABS ... ... ALGO TE DC load 50 - 150 ms 15 1 ms < 120 uA < 0.5 mA (optional) Current wetting pulse (Refer to SIN227) TE AC load 20 5 ms Note 1 Zss (Refer to SIN227) Note 2 FSKE Note 3 FCDN FDRN ... ... A >= 100 ms B = 88 - 110 ms C >= 45 ms (up to 5 sec) D = 80 - 262 ms E = 45 - 75 ms F <= 2.5 sec (500 ms typical) G >= 200 ms DCLK DATA ...101010... Data Figure 9-5. Input and Output Timing of BT Idle State (On-hook) Data Transmission Notes: 1. SIN227 specifies that the AC and DC loads should be applied at 20 5 mS after the end of the dual tone alert signal. 2. SIN227 specifies that the AC and DC loads should be removed between 50-150 mS after the end of the FSK signal. The W91030B may also be placed in a sleep condition. 3. The FSKE pin should be set low to disable the FSK demodulator when FSK is not expected. The tone alerting signal speech and the DTMF tones are in the same frequency band as the FSK signal. If the FSKE pin can not controlled by microcontroller, the FSKE pin must always placed in high state and the microcontroller must give up the FSK decoded data when the FSK signal is not expected. 4. The W91030B may not be woken up at this ring signal after the FSK data has been processed. - 26 - Preliminary W91030B CPE goes off-hook Start Point CPE mutes handset & disables keypad CPE sends ACK D Mark F Message G CPE unmutes handset and enables keypad Tip/Ring Note 1 A Note 3 Alert Signal B C E Note 6 H SLEEP INTN tREC tABS ... ALGO FSKE Note 2 Note 4 Note 5 FCDN FDRN ... DCLK DATA Data Figure 9-6. Input and Output Timing of BT Loop State (Off-hook) Data Transmission A = 40-50 mS C = 100 mS E = 5-100 mS G = Depends on data length Notes: B = 80-85 mS D = 65-75 mS F = 45-75 mS H 100 mS 1. In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and use battery power while on-hook. 2. The FSKE pin may be set low to prevent the alert tone, speech or other FSK inband noise decoded by FSK demodulator and give false data when the dual tone alert signal is expected. If the FSKE pin can not controlled by microcontroller, the FSKE pin must always placed in high state and the microcontroller must give up the FSK decoded data when the FSK signal is not expected. 3. The exchange will have already disabled the speech path to the distant customer in both transmission directions. 4. The FSKE should be set high as soon as the CPE has finished sending the acknowledge signal ACK. 5. The FSKE may be set low after the last byte (check sum) has been decoded or FCDN has become inactive. 6. In unsuccessful attempts where the exchange does not send the FSK signal, the CPE should disable FSKE, unmute the handset and enable the keypad after this interval. - 27 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B Line Reversal First Ring Cycle Ch. Seizure C Mark D Message E A/B Wires Ring Burst A B F RNGON SLEEP Note 4 INTN ... 250 - 400 mS ... 50 - 150 mS TE DC load TE AC load Note 2 Note 3 FSKE Note 1 FCDN FDRN ... ... A = 200 - 450 mS B >= 500 mS C = 80 - 262 mS D = 45 - 262 mS E <= 2.5 sec (500 mS typical) F >= 200 mS DCLK DATA ...101010... Data Figure 9-7. Input and Output Timing of CCA Caller Display Service Data Transmission Notes: 1. The CPE designer may choose to set FSKE always high while the the CPE is on-hook and the FSK signal is expected. 2. TW/P & E/312 specifies that the AC and DC loads should be applied between 250-400 mS after the end of the ring burst. 3. TW/P & E/312 specifies that the AC and DC loads should be removed between 50-150 mS after the end of the FSK signal. The W91030B may also be placed in a sleep condition. 4. The W91030B may not be woken up at the first ring cycle after the FSK data had been processed. - 28 - Preliminary W91030B PACKAGE DIMENSIONS 24L PDIP-600mil D 24 13 1 E 1 12 S 2 E c A 1 A L A Base Plane Seating Plane B B1 e1 \ eA Dimension in inches Dimension in mm Min. Nom. Max. 5.33 0.25 3.81 0.41 1.47 0.20 3.94 0.46 1.52 0.25 4.06 0.56 1.63 0.36 Symbol Min. Nom. Max. 0.210 A A1 A2 B B1 c D E E1 e1 L \ 0.010 0.150 0.155 0.160 0.016 0.018 0.022 0.058 0.060 0.064 0.014 1.260 0.008 0.010 1.250 31.75 32.00 15.49 0.590 0.600 0.610 14.99 15.24 0.545 0.550 0.555 13.84 13.97 14.10 0.090 0.100 0.110 0.120 0.130 0.140 0 15 2.29 3.05 0 2.54 3.30 2.79 3.56 15 16.51 17.02 2.16 eA S 0.630 0.650 0.670 16.00 0.085 - 29 - Publication Release Date: March 2000 Revision A1 Preliminary W91030B Package Dimensions, continued 24L SOP-300mil 24 13 c E HE L 1 D 12 0.25 O A Y SEATING PLANE b Control demensions are in milmeters. SYMBOL A A1 b c E D e HE Y L Dimension in mm MIN. MAX. 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 7.40 15.20 7.60 15.60 1.27 BSC 10.65 10.00 0.10 0.40 1.27 0 8 Dimension in Inches MIN. MAX. 0.093 0.104 0.012 0.004 0.013 0.020 0.013 0.299 0.614 0.050 BSC 0.394 0.419 0.004 0.016 0.050 0 8 0.009 0.291 0.598 e A1 GAUGE PLANE - 30 - Preliminary W91030B Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 31 - Publication Release Date: March 2000 Revision A1 |
Price & Availability of W91030
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |